Position: Mid-Senior level

Job type: Full-time

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Job content

Our customer is a global leader in optical solutions offering an unique product and technology portfolio for sensing, illumination and visualization, from prime-quality light emitters and optical components to micro-modules, light sensors, ICs and related software.

As trusted partner serving the entire value chain of optical solutions, our customer enables supports to its clients in the consumer, automotive, industrial, and healthcare sectors maintain their competitive edge, adding intelligence to light and passion to innovation to enrich people’s lives.

For its center of technical excellence based in Pavia is looking for a




The best Candidate has a degree in Electronic Engineering, with at least 5 / 8 years of experience in digital design/verification with hands-on experience on relevant design/simulation tools. He / She is teamwork oriented and proactive, as well as fluent in English.

Essential Duties and Responsibilities:
  • Perform digital design writing RTL code in Verilog/VHDL
  • Prepare testbenches for RTL verification run regression
  • Prepare and contribute to technical documentation such as device specification simulation reports
  • Support lab validation and production test program development
  • Execute Digital verification with Wreal models, UVM assertions
  • Contribute to verification strategy definition generation of verification plans for complex mixed signal or digital devices
  • Promote development of verification environment and ensure proper verification coverage for enabling bug free silicon manufacturing
  • Foster realization of DV test cases and debugging of simulation result

Essential Requirements:
  • University Master degree in electronic engineering and 5 / 8 years of relevant experience
  • Knowledge of design verification methodologies, tools and languages (Digital Mixed-Signal simulation, UVM, SystemVerilog, assertions …)
  • Experience in analog blocks modeling
  • Knowledge of CDC/LINT/LEC check
  • Knowledge of RTL design with HDL (Verilog/VHDL) for integrated devices.
Altre informazioni:

Place of work: Pavia + smart working
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Deadline: 24-06-2023

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